library verilog;
use verilog.vl_types.all;
entity SR_169 is
    port(
        reset           : in     vl_logic;
        parallel_input  : in     vl_logic_vector(3 downto 0);
        parallel_enable : in     vl_logic;
        Q               : out    vl_logic_vector(3 downto 0);
        clock           : in     vl_logic;
        count_en        : in     vl_logic;
        TC              : out    vl_logic;
        up_downbar      : in     vl_logic
    );
end SR_169;
